StuBS
LAPIC::IPI::InterruptCommand Union Reference

Interrupt Command. More...

Classes

struct  [struct].__unnamed0__
struct  [struct].__unnamed1__
 I/O redirection-table entry. More...

Public Member Functions

 InterruptCommand ()=default
 Default constructor.
 InterruptCommand (uint8_t destination, uint8_t vector=0, DestinationMode destination_mode=DestinationMode::PHYSICAL, DeliveryMode delivery_mode=DeliveryMode::FIXED, TriggerMode trigger_mode=TriggerMode::EDGE_TRIGGERED, Level level=Level::ASSERT)
 InterruptCommand (DestinationShorthand destination_shorthand, uint8_t vector, DeliveryMode delivery_mode=DeliveryMode::FIXED, TriggerMode trigger_mode=TriggerMode::EDGE_TRIGGERED, Level level=Level::ASSERT)
void send () const
bool isSendPending ()

Public Attributes

struct  
struct  

Private Member Functions

void readRegister ()

Detailed Description

Interrupt Command.

See also
ISDMv3 10.6.1 Interrupt Command Register (ICR)

Class Documentation

◆ LAPIC::IPI::InterruptCommand::[struct].__unnamed0__

struct LAPIC::IPI::InterruptCommand::[struct].__unnamed0__
Class Members
uint64_t vector: 8 Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers.

Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers.

enum DeliveryMode delivery_mode: 3 The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs.

For StuBS, we use DeliveryMode::LowestPriority, as all CPU cores have the same priority and we want to distribute interrupts evenly among them. It, however, is not guaranteed that this method of load balancing will work on every system.

enum DestinationMode destination_mode: 1 The destination mode defines how the value stored in destination will be interpreted.

For StuBS, we use DestinationMode::Logical.

enum DeliveryStatus delivery_status: 1 Delivery status holds the current status of interrupt delivery.
Note
This field is read only; write accesses to this field will be ignored.
uint64_t __pad0__: 1 reserved
enum Level level: 1 The polarity denotes when an interrupt should be issued.

For StuBS, we use Polarity::High (i.e., when the interrupt line is, logically, 1).

enum TriggerMode trigger_mode: 1 The trigger mode states whether the interrupt signaling is level or edge triggered.

StuBS uses TriggerMode::Edge for Keyboard and Timer, the (optional) serial interface, however, needs TriggerMode::Level.

uint64_t __pad1__: 2 reserved
enum DestinationShorthand destination_shorthand: 2
uint64_t __pad2__: 36 Reserved, do not modify.
uint64_t destination: 8 Interrupt destination.

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores, see Core::count() ). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Note
This form of load balancing depends on the hardware's behavior and may not work on all systems in the same fashion. Most notably, in QEMU all interrupts are sent to the BSP (core 0).

◆ LAPIC::IPI::InterruptCommand::[struct].__unnamed1__

struct LAPIC::IPI::InterruptCommand::[struct].__unnamed1__

I/O redirection-table entry.

Every entry in the redirection table represents an external source of interrupts and has a size of 64 bits. Due to the I/O APIC registers being only 32 bits wide, the 64-bit value is split in two 32 bit values.

Class Members
Register value_low First, low-order register.
Register value_high Second, high-order register.

Constructor & Destructor Documentation

◆ InterruptCommand() [1/3]

LAPIC::IPI::InterruptCommand::InterruptCommand ( )
default

Default constructor.

◆ InterruptCommand() [2/3]

LAPIC::IPI::InterruptCommand::InterruptCommand ( uint8_t destination,
uint8_t vector = 0,
DestinationMode destination_mode = DestinationMode::PHYSICAL,
DeliveryMode delivery_mode = DeliveryMode::FIXED,
TriggerMode trigger_mode = TriggerMode::EDGE_TRIGGERED,
Level level = Level::ASSERT )
inlineexplicit

◆ InterruptCommand() [3/3]

LAPIC::IPI::InterruptCommand::InterruptCommand ( DestinationShorthand destination_shorthand,
uint8_t vector,
DeliveryMode delivery_mode = DeliveryMode::FIXED,
TriggerMode trigger_mode = TriggerMode::EDGE_TRIGGERED,
Level level = Level::ASSERT )
inline

Member Function Documentation

◆ send()

void LAPIC::IPI::InterruptCommand::send ( ) const
inline

◆ isSendPending()

bool LAPIC::IPI::InterruptCommand::isSendPending ( )
inline

◆ readRegister()

void LAPIC::IPI::InterruptCommand::readRegister ( )
inlineprivate

Member Data Documentation

◆ @232347234376033112226227176372256231135002331201

struct LAPIC::IPI::InterruptCommand::[struct].__unnamed0__ LAPIC::IPI::InterruptCommand

◆ @233067063112035065034001256143131362373121056153

struct LAPIC::IPI::InterruptCommand::[struct].__unnamed1__ LAPIC::IPI::InterruptCommand
The documentation for this union was generated from the following file: